1. Field of the Invention
The present invention relates to a multilayer wiring substrate having a multilayer structure in which a plurality of resin insulation layers and a plurality of conductor layers are laminated alternately.
2. Description of Related Art
In association with recent increasing tendency toward higher operation speed and higher functionality of semiconductor integrated circuit devices (IC chips) used as, for example, microprocessors of computers, the number of terminals increases, and the pitch between the terminals tends to become narrower. Generally, a large number of terminals are densely arrayed on the bottom surface of an IC chip and flip-chip-bonded to terminals provided on a motherboard. However, since the terminals of the IC chip differ greatly in pitch from those of the motherboard, difficulty is encountered in bonding the IC chip directly onto the motherboard. Thus, according to an ordinarily employed method, a semiconductor package configured such that the IC chip is mounted on an IC chip mounting wiring substrate is fabricated, and the semiconductor package is mounted on the motherboard.
The IC chip mounting wiring substrate which partially constitutes such a semiconductor package is practicalized in the form of a multilayer substrate configured such that a build-up layer is formed on the front and back surfaces of a substrate core. The substrate core used in the multilayer wiring substrate is, for example, a resin substrate (glass epoxy substrate or the like) formed by impregnating reinforcement fiber with resin. Through utilization of rigidity of the substrate core, resin insulation layers and conductor layers are laminated alternately on the front and back surfaces of the substrate core, thereby forming respective build-up layers. In the multilayer wiring substrate, the substrate core serves as a reinforcement and is formed very thick as compared with the build-up layers. Also, the substrate core has conductor lines (specifically, through-hole conductors, etc.) extending therethrough for electrical communication between the build-up layers formed on the front and back surfaces.
In recent years, in association with implementation of high operation speeds of semiconductor integrated circuit devices, signal frequencies to be used have become those of a high frequency band. In this case, the conductor lines which extend through the substrate core serve as sources of high inductance, leading to the transmission loss of high-frequency signals and the occurrence of circuitry malfunction and thus hindering implementation of high operation speed. In order to solve this problem, a multilayer wiring substrate having no substrate core is proposed. Such a multilayer wiring substrate does not use a substrate core, which is relatively thick, thereby reducing the overall wiring length. Thus, the transmission loss of high-frequency signals is lowered, whereby a semiconductor integrated circuit device can be operated at high speed.
However, since the strength of such a substrate is insufficient because of omission of the substrate core, the substrate is apt to warp. In order to avoid such warpage, there has been proposed a multilayer wiring substrate in which some of a plurality of resin insulation layers contain a reinforcement material (refer to, for example, Patent Document 1). Specifically, in the multilayer wiring substrate disclosed in Patent Document 1, an insulation layer containing a reinforcement material is provided at the center of the substrate with respect to the lamination direction, or is provided on each of the top and bottom surfaces of the substrate.